1. Field of the Invention
The present invention relates to an interface circuit for a semiconductor memory device such as a memory card, a memory pack or the like, and more particularly, it relates to technique of optimizing the control procedure of power supply and bus signals for such a semiconductor memory device.
2. Description of the Background Art
A memory card serving as a semiconductor memory device is widely applied to a small word processor, a lap-top personal computer or the like as a high-speed small recording medium of a detachable type.
FIG. 5 is a circuit diagram showing the structure of a conventional interface circuit for a semiconductor memory device. Referring to FIG. 5, a semiconductor memory device 101 such as a DRAM, SRAM, EEPROM or the like is detachably connected with a terminal device 150 through a power supply terminal V.sub.CC, an address terminal T.sub.A, a control terminal T.sub.C and a data input/output terminal T.sub.D. The terminal device 150 comprises a CPU (not shown) and an interface circuit 151 for the CPU and the semiconductor memory device 101. A supply voltage V.sub.C is inputted in a power input line 111 of the interface circuit 151 from a power supply (not shown). The power input line 111 is connected to an emitter of a transistor 102, which is adapted to connect/cut off the supply voltage V.sub.C, as well as to a base of the transistor 102 through a bleeder resistor 103. The bleeder resistor 103 is adapted to raise up the base potential of the transistor 102 to the supply voltage V.sub.C. A control signal line 118, which receives a power supply/bus control signal VBC for controlling the power supply and buses, is connected to an input terminal of an inverter 106. This control signal line 118 is further connected to a gate terminal G of a three-state unidirectional buffer (hereinafter simply referred to as "buffer") 107 and a gate terminal G of a three-state bidirectional buffer (hereinafter simply referred to as "buffer") 108. An output terminal of the inverter 106 is connected to the base of the transistor 102 through a base resistor 104. The base resistor 104 is adapted to control the base current of the transistor 102. The collector of the transistor 102 is connected to the power supply terminal V.sub.CC of the semiconductor memory device 101, while an end of an input resistor 105, another end of which is grounded, is connected to an intermediate node therebetween. The input resistor 105 is adapted to determine input impedance to the semiconductor memory device 101 when the transistor 102 is cut off.
The buffer 107 is interposed in an address bus 113, which is connected to the address terminal T.sub.A of the semiconductor memory device 101, and a control bus 114, which is connected to the control terminal T.sub.C of the semiconductor memory device 101. Address data ADD are inputted in the semiconductor memory device 101 through the address bus 113, while control data CTD are inputted in the semiconductor memory device 101 through the control bus 114. The buffer 107 connects/cuts off inputs of the address data ADD and the control data CTD in response to the power supply/bus control signal VBC.
The buffer 108 is interposed in a data bus 115, which is connected to the data input/output terminal T.sub.D of the semiconductor memory device 101. A data signal DTS is inputted in or outputted from the semiconductor memory device 101 through the data bus 115. The buffer 108 connects/cuts off input/output of the data signal DTS in response to the power supply/bus control signal VBC. A direction switching signal line 116 is connected to a direction switching terminal DIR of the buffer 108. The direction switching signal line 116 is supplied with a read/write signal R/W, in order to switch the direction of movement of the data signal DTS in the buffer 108 in response to read/write operation of the semiconductor memory device 101.
Operation timing of the conventional interface circuit 151 having the aforementioned structure is now described.
FIG. 6 is an operation timing chart of the conventional interface circuit 151.
When a power supply/bus control signal VBC of a high level is applied to the control signal line 118, the gate terminals G of both buffers 107 and 108 go high so that the buffers 107 and 108 enter enable states and conduct. Due to such conduction, the address data ADD, the control data CTD and the data DTS received in the buses 113, 114 and 115 are supplied to the semiconductor memory device 101.
When such a high-level power supply/bus control signal VBC is applied to the control signal line 118, further, the output of the inverter 106 goes low. Therefore, a base current flows to the transistor 102 through the base resistor 104 to allow conduction of the transistor 102, whereby a supply voltage V.sub.C ' is supplied to the power supply terminal V.sub.CC.
In general, the speed and time required for connecting/cutting off the buffers 107 and 108 are higher and shorter than those required for connecting/cutting off the transistor 102. Namely, the buffers 107 and 108 conduct in advance of the transistor 102 in response to the change of the power supply/bus control signal VBC from a low level to a high level (FIG. 6(a)). Therefore, data ADD', CTD' and DTS' are supplied from the respective buses 113, 114 and 115 to the terminals T.sub.A, T.sub.C and T.sub.D of the semiconductor memory device 101 in advance of the supply voltage V.sub.C ' (FIG. 6(b) and (c)).
When a power supply/bus control signal VBC of a low level is applied to the control signal line 118, on the other hand, the gate terminals G of the buffers 107 and 108 enter disable states, whereby the buffers 107 and 108 are cut off. Further, the output of the inverter 106 goes high to cut off the transistor 102. Therefore, the data ADD, CTD and DTS and the supply voltage V.sub.C are not supplied to the terminals V.sub.CC, T.sub.A, T.sub.C and T.sub.D. Since the time required for connecting/cutting off the buffers 107 and 108 is shorter than that for the transistor 102 as hereinabove described, the transistor 102 is cut off after the buffers 107 and 108 are cut off.
In such a semiconductor memory device having a semiconductor integrated circuit in its interior, it is generally desired to first input a power supply, thereafter add an input/output signal, cut off the input signal and thereafter cut off the power supply.
When data supply to the buses is stopped in the conventional interface circuit shown in FIG. 5, the supply voltage is cut off in a delay to the bus data to with no problem, since the transistor is cut off after the buffers are cut off, as hereinabove described. When the bus data are supplied to the semiconductor memory device as shown in FIG. 6, however, difference of a time t.sub.2 is caused between conduction of the buses and conduction of the power supply, and hence the bus data are problematically inputted in advance of the supply voltage by the time t.sub.2. When the bus data are thus precedingly inputted, a latch-up phenomenon may take place such that the semiconductor integrated circuit provided in the semiconductor memory device performs no normal storage operation, and an excess current may flow due to such a latch-up phenomenon as the case may be, to deteriorate and break the internal semiconductor integrated circuit. Thus, it is not desirable for the semiconductor memory device that the buses conduct in advance of the power supply.